Semiconductor Energy Laboratory (SEL) and Silvaco have jointly developed a SPICE model of oxide semiconductor FETs (field effect transistor) for use in a variety of applications, including the AI (artificial intelligence) field.
The crystalline oxide semiconductor CAAC-IGZOⓇ FET (c-axis aligned crystalline indium-gallium-zinc oxide FET) developed by SEL has extremely low off-leakage current, which enables ultra-low power consumption of semiconductors including memory and integrated circuits.
The new semiconductor device is expected to be a key device in helping with reducing power consumption in the coming AI era. Until now a compact model for SPICE simulation, essential for circuit design, was not available and it has been difficult to reproduce detailed circuit characteristics through simulation.
The jointly developed compact model for CAAC-IGZO FET is a charge-based model that extends the material characteristics and operation mode of CAAC-IGZO FET and is based on BSIM-CMG, which is the industry standard model for multi-gate FinFET. The new compact model can faithfully reproduce the characteristics of oxide semiconductor FET.
Advantages of the compact model
Modeling of operation in the oxide semiconductor’s accumulation mode
Modeling of L/W scalability and temperature dependence
Support of multi-gate structure with Fin shape
Modeling of threshold voltage control by bottom gate
Modeling of interface trapped charge and sub-gap localized charge
Implemented in industry standard Verilog-A language
SEL and Silvaco presented a paper on the compact model of CAAC-IGZO FET at the EDTM2021 conference held in Chengdu, China, April 8-11. For more information about the paper, please visit EDTM2021.
https://ewh.ieee.org/conf/edtm/2021/
The new SPICE model card has been generated by Silvaco’s SPICE model extraction tool Utmost IV with the measured data from SEL and has been verified with Silvaco’s high-performance circuit simulator, SmartSpice. This model will be used by partners who use SEL’s CAAC-IGZO FET technology.
Takayuki Ikeda, General Manager of the CD Division at SEL, said, “The CAAC-IGZO FET has a back gate, and the current can be controlled independently of the top gate. However, the design has been limited by the lack of a suitable model for circuit simulation. To eliminate this limitation, we partnered with Silvaco to develop a model for CAAC-IGZO FET. We hope that the new model will be adopted by the industry and enable wide adoption of CAAC-IGZO FET.”
Naoto Kameda, General Manager of Silvaco Japan, said, “We are very proud to have collaborated with SEL. They have many years of experience and advanced knowledge in oxide semiconductor technology, to develop a compact model which has been one of the challenges in oxide semiconductor research and development. We look forward to the wide adoption of this SPICE model in many applications developed by CAAC-IGZO FET technology.”
