Arasan Chip Systems, a specialist provider of semiconductor IP for mobile and automobile SoCs, lately announced the immediate availability of its I3C Dual/Secondary Controller IP which now includes the I3C PHY IP.
Arasan expands its MIPI IP portfolio with the announcement of the immediate availability of its I3C Dual/Secondary Controller IP including I3C PHY compliant with MIPI I3C HCI Specification (v1.2).
The I3C PHY supports the Ternary and non Ternary modes and is available on foundry nodes from 28nm to 4nm.
The Arasan I3C Secondary Controller IP Core implements Active controller functionality as defined by the MIPI Alliance’s I3C Specification and Secondary Controller logic. The I3C bus is used for various sensors in the mobile/automotive system where the active controller transfers data and control between itself and various sensor devices.
In some applications, the active controllers can hand-off the controller role to the secondary controller on the bus. The Dual role IP joins the I3C bus as a secondary controller (as a target) and will request/accept the controller role.
The IP core provides a 32bit AHB bus as an application interface to configure and control the transfers. The controller manages the control signal to IO buffers during the active and standby mode.
The I3C Dual Role controller is available for immediate licensing.
