EMASS has received the first engineering samples of its next-generation 16nm ECS-DoT edge AI SoC from TSMC. The design that was signed off in December 2025 and taped out in January 2026 has now been manufactured on TSMC’s 16nm FinFET process and is in the hands of the EMASS engineering
team.
Receipt of first silicon is a major technical milestone for the company and the first time
an ECS-DoT device has been produced at an advanced FinFET node. It is the point at which a chip program stops being a design and becomes a product. Everything before it, from architecture and RTL through synthesis, physical design and GDS sign-off, is work on a description of the chip. What EMASS holds today is the chip itself.
The 16nm ECS-DoT program reached this point in sequence. Front-end design, synthesis and
physical design were completed and the design entered final GDS sign-off in December 2025.
Tape-out followed in January 2026, when the mask data was released to TSMC and wafer
fabrication began. The wafers have since been processed, diced and assembled into packaged
engineering samples, which have now been delivered to EMASS.
The 16nm FinFET is an advanced node for ultra-low-power edge AI silicon. Moving to FinFET brings
higher logic density, lower leakage and more headroom for on-chip integration, which is what
allowed EMASS to place a full radio, a larger memory array and additional accelerators on the
same die while holding to the power budget the ECS-DoT family was designed around.
EMASS now has ECS-DoT silicon at two process nodes, and the two devices are intended to
do different, yet overlapping jobs. The 22nm ECS-DoT is the company’s commercial product and the device customers can design with today. It is in customer evaluation and design-in across wearables, industrial sensing, asset tracking, smart infrastructure and other always-on applications, including the asset tracking reference design with Bosch Sensortec announced in July 2026.
The 16nm ECS-DoT is the more fully integrated member of the family. It is aimed at customers
who need more on-chip memory, who want to run vision alongside audio and sensor
workloads, or who want the Bluetooth radio inside the SoC rather than as a separate part on
the board. Both devices share one programming model, software stack and toolchain, so a
customer can start on 22nm today and move to 16nm later with minimal changes to
application code, and EMASS can support both from a single engineering base.
This is the position an established semiconductor company works from: a commercial device
winning design-ins while the next generation is characterised behind it. It is the first time
EMASS has held both at once.
What Is on the 16nm Chip
The 16nm ECS-DoT retains the RISC-V core, dual deep-learning accelerators, scalable
compute-to-memory interconnect and always-on design philosophy of the 22nm generation.
- Integrated Bluetooth Low Energy subsystem. The full BLE signal chain, including the
analog front end, RF transceiver, phase-locked loops and on-chip matching networks, is
built into the SoC. In many designs this removes the need for a separate wireless chip,
cutting board area, bill-of-materials cost and design complexity for connected devices
such as wearables, tags and industrial sensors.
- Expanded on-chip SRAM. A substantial increase in on-chip memory supports larger
neural networks and higher-throughput vision and multi-sensor workloads, and reduces
the off-chip memory accesses that dominate energy consumption in many edge AI
systems.
- Adaptive fine-grained power-management fabric. EMASS’s most advanced power
architecture to date, with fine-grained power gating across functional domains, dynamic
clock gating and autonomous low-power states managed by internal controllers, giving
microsecond-level sleep and wake behaviour for always-on monitoring in wearables,
smart tags, industrial sensors and environmental monitoring. The design achieves this
without dynamic voltage and frequency scaling, relying instead on architectural and
circuit-level techniques.
Dedicated AI acceleration module for object detection. A purpose-built engine for
lightweight vision models such as YOLO-Nano class networks, MobileNet-SSD detection
heads and FOMO-style detectors.
It offloads detection from the main cores to raise throughput and cut inference latency in applications such as drones, smart cameras, safety systems and industrial inspection. The non-maximum suppression stage of this module is the subject of US Patent No. 12,651,452 B2, exclusively licensed to EMASS, as
announced on 1 September 2026.
Continuing to Smaller Nodes
Delivering an ultra-low-power edge AI SoC at 16nm FinFET demonstrates that EMASS can take
the ECS-DoT architecture to an advanced node; the characterisation program will now
quantify what the move delivers in power and performance.
EMASS has now taken two designs through TSMC, at 22nm and 16nm, and has established the design, verification and physical design capability, including the recently established engineering centre in Cairo, to keep doing so. The company continues to evaluate smaller process nodes for future
generations of ECS-DoT, and intends to remain at the front of the category in bringing always
on intelligence onto more advanced silicon.
Director of Nanoveu and Founder of EMASS, Dr Mohamed Sabry, said: “There is a particular
moment in every chip program when the first parts come back from the fab and you can hold
what was, until then, a set of files. We have reached that moment with the 16nm ECS-DoT. It
carries everything we set out to build: the radio, the memory, the power fabric, the detection
engine and the FPU, on one die at 16nm. Now the real work of measuring it starts, and we will
report what the silicon tells us.”
Nanoveu will provide further updates as the 16nm ECS-DoT progresses through bring-up,
benchmarking and characterisation.
